• Profile
  • LTE RAN RF TUNING ENGG
  • The University of Texas at Dallas
  • Dallas/Fort Worth
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  • Professional Experience

    2010 - Present
    2005 - 2007
    Module-lead for a team of 3+ in the C#(.Net) based development and testing project with My-SQL (2000/2005), and Power Builder as the thick client.Developed web-based three tier applications namely SMS, E-Bank Works, E-Credit, ATM and E-Treasury (banking solutions). Coded in C# .NET, ASP .NET, JavaScript, Q++ and PL/SQL.Fixed high priority production issues and change management requests in .NET applications in a highly critical banking environment and ensured optimization of the code.Worked with MS SQL database and developed stored procedures.Provided level 3 technical supports for the client in live production. Have received appreciation from the client and top management in TCS for the support given during critical production issues.Involved in deploying and building the application in the production environment.Optimized performance of SQL queries using SQL Profiler, SQL Query Analyzer and identified suitable indexes and query optimization measures.Integrated around 180 branches in a period of 2 years and interfaced the bank with the ATM. The net profit grew up to 24 % in the same year and 50 % the following year.Real Time Gross Settlement (RTGS) computerized the wire transfer across all the branches (that initially took 3 days) and reduced operation costs and increased timeliness.Presented and reviewed documents as a part of project policy.INDUSTRIAL INTERNS
  • Educational Background

    2008 - 2010

    VLSI Design: Implementation of Low Power First Order Linear Interpolator using CMOS 0.13um technology.Advance VLSI design: 1) Design and layout of a 512b SRAM using the IBM 130nm process. Cadence’s Virtuoso for layout editing, DRC, LVS were used. 2) Design implementation of High radix 12-bit Divider circuit using HSPICE, Encounter tool and Pathmill.ASIC: Digital filter design used for Mini Stereo Digital Audio Processor (MSDAP) using C and VHDL programming. Computer Architecture:Branch Predictors and their types (Gshare, Tournament and a novel predictor ‘Gskew’) by simulating C code using SimpeScalar tool. Testing and Testable design: ATE, Boundary scans, BIST. Assignments using TetraMax test generators were done. DSP Architectures: FFT filter design using TI (C6x) kit, ARM processors, TigerSHARC and DLX architectures.Optical Communication System: Design of optical transmission of 400Gbs data over 3500 km single fiber using WDM mode using OPTSim.

    Extra-activity: Indian student Association

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