Barry Davis

Low Cost Data Streaming Mechanism

Application

#6460108 Oct 1, 2002

Filed

Mar 31, 1999

Inventor

Jeff J. McCoskey (Phoenix, AZ) · Richard P. Mackey (Phoenix, AZ) · Barry R. Davis (Portland, OR)

Appl. No.

09/282386

Assignee

Intel Corporation (Santa Clara, CA)

International Classification

G06F 1300

U.S. Classification

710310, 710 57, 710305, 710306, 710307

Abstract

A method and apparatus for providing an efficient, low cost data streaming mechanism from a first bus architecture to a second bus architecture across a bus bridge. Separate read and write data...

Claim

What is claimed is: 1. A method for data streaming comprising: a) detecting a write transaction on a first bus that is targeted to a second bus, wherein the second bus is operating at a faster speed...

Methods And Apparatus To Correct Duty Cycle

Application

#6981185 Dec 27, 2005

Filed

Aug 9, 2002

Inventor

Barry Allen Davis (Union City, CA) · Walter F. Bridgewater (San Jose, CA)

Appl. No.

10/215919

Assignee

Adaptec, Inc. (Milpitas, CA)

International Classification

G06F011/00

U.S. Classification

714707, 714709

Abstract

An apparatus for correcting duty cycle error is provided which includes circuitry capable of determining existence of a duty cycle error from input data received over data transmissions lines where...

Guitar Playing Assist Apparatus

Application

#7468478 Dec 23, 2008

Filed

Aug 12, 2004

Inventor

Barry Mark Davis (Perkinston, MS)

Appl. No.

10/916575

Assignee

Barry Mark Davis (Perkinston, MS)

International Classification

G10D 3/00

U.S. Classification

84290

Abstract

A thin flat body of clear plastic with a key pad () on the inside back base (), and a chord scale () on the outside front of the base (). The chord scale is fitted with braille nodules () for guiding ...

Method And Apparatus For Maintaining Coherency For Data Transaction Of Cpu And Bus Device Utilizing Selective Flushing Mechanism

Application

#6021473 Feb 1, 2000

Filed

Aug 27, 1996

Inventor

Barry M. Davis (Phoenix, AZ) · Nicholas J. Richardson (La Jolla, CA) · Brian N. Fall (Chandler, AZ)

Appl. No.

8/703677

Assignee

VLSI Technology, Inc. (San Jose, CA)

International Classification

G06F 1200, G06F 1300

U.S. Classification

711141

Abstract

A method and apparatus for maintaining coherency in CPU and bus device data transactions in a computer system. A CPU may write data items to a memory shared with bus devices and may also write data...

Deadlock Resolution Methods And Apparatus For Interfacing Concurrent And Asynchronous Buses

Application

#5761454 Jun 2, 1998

Filed

Aug 27, 1996

Inventor

Swaroop Adusumilli (Tempe, AZ) · Barry M. Davis (Phoenix, AZ) · Brian N. Fall (Chandler, AZ) · Nicholas J. Richardson (La Jolla, CA) · Philip Wszolek (Phoenix, AZ)

Appl. No.

8/703563

Assignee

VLSI Technology, Inc. (San Jose, CA)

International Classification

G06F 1336

U.S. Classification

395306

Abstract

A deadlock detection and resolution circuit for resolving a deadlock condition in a bridge circuit coupled to a memory, a host bus and a PCI bus of a computer system. The host bus and the PCI bus are ...

Method And Apparatus Providing An Improved Pci Bus System

Application

#6324609 Nov 27, 2001

Filed

Aug 12, 1998

Inventor

Barry R. Davis (Scottsdale, AZ) · Scott Goble (Chandler, AZ)

Appl. No.

9/132737

Assignee

Intel Corporation (Santa Clara, CA)

International Classification

G06F 13368

U.S. Classification

710119

Abstract

A PCI-to-PCI bridge having a processor configured for performing various routing mode operations based upon the addresses of transactions carried on interconnected PCI buses. The various routing...