• Professional Experience
    2012 - Present
    2010 - 2012
    2009 - 2010
    2007 - 2008
    Principal Designer of a parametrizable BIST microcontroller for testing different memories. Synthesizing, floor planning, power planning and place and routing in TSMC 90nm and IBM 65nm std cell libraries using Cadence Nano-Encounter, RTL Compiler and Synopsys DC Compiler and Astro. Automating the entiredesign flow using Perl. Successfully post-fabrication testing. Cooperating in design and verification of different embedded memories such as DRAMs and SRAMs.
    Show All Professional Experiences (1)
  • Educational Background
    Show All Educational Background (2)
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