• Professional Experience
    2007 - Present
    I lead the system architecture team for three generations of the Tegra applications processor. I am responsible for the overall system, memory controller and system buses, CPU, peripheral controllers, DMA paths, high speed peripherals and flash memory controllers. I manage technical engagement with ARM and maintain a strong relationship with them for the world’s first Cortex-A9 design. I guide development of multiple blocks, and instilled processes for low power and high performance.
    2004 - 2007
    I recruited and led a team to develop the world’s lowest power hardware video decoder, as part of the CTO’s technology group. I led this design through tape out. This was key technology that led to NVIDIA’s purchase of PortalPlayer, and is still in use in Tegra today.
    2001 - 2004
    Led the HW design teams of two generations of the NForce 3 chip-set used with the AMD K8 CPU. Managed the chip design process through concept, development, verification, timing closure, bring-up and release to manufacturing.
    1995 - 2001
    Start-up that created a multi-core VLIW media processor. I led system architecture, designed and brought to production this highly innovative device. I also led a software team that delivered production DVD player software to Toshiba and Samsung.
    1989 - 1994
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